Computer Architecture and Parallel Processing
Some of Our Papers
- Fine Grain Parallel Processors
- T. Arita, H. Takagi and M. Sowa, "V++: An Instruction-Restructurable Processor Architecture", Proceedings of the Twenty-Seventh Annual Hawaii International Conference on System Sciences, Vol. I (ARCHITECTURE), pp.398-407, 1994. (abstract)
- Scheduling Methods
- Takaya ARITA, Hiromitsu TAKAGI and Masahiro SOWA, "Efficient Multiprocessor Scheduling Based on Bidirectional Complement Hypothesis and Building Block Hypothesis", Joint Symposium on Parallel Processing 1993 (JSPP '93), pp. 283-290, 1993 (in Japanese)D (abstract)
- Synchronization Mechanisms
- T. Arita and M. Sowa, "High Speed Synchronization for a Statically Scheduled Superscalar Processor", International Journal of High Speed Computing, Vol. 3, No. 1, pp. 77-87, World Scientific, 1991. (abstract)